Currently there is difficulty in maintaining semiconductor device performance improvements in devices of deeply submicron generations. To maintain such improvements, the use of a self-aligned contact (SAC) may be inevitable for semiconductor devices of 14 nm nodes and beyond due to increasingly scaled gate pitches. The use of a SAC typically requires an insulator cap to electrically isolate the SAC from the gate conductor. As such, parasitic capacitance is formed by the gate conductor, the insulator cap, and the SAC. This parasitic capacitance may adversely impact device performance and power consumption. However, conventional gate caps utilized to reduce this parasitic capacitance may have poor etch selectivity to, for example, oxide and nitride which are widely used in device fabrication. Thus, direct usage of these conventional gate caps introduces fabrication problems. Therefore, there is a need to improve semiconductor device SAC fabrication process and structures.